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22713hk/53012hkim 20120426-s00003 no.a2055-1/19 ver.1.01 semiconductor components industries, llc, 2013 february, 2013 http://onsemi.com LC87F0N04A overview the LC87F0N04A is an 8-bit microcomputer that, integrates on a single chip a number of hardware features such as 4.5k-byte flash rom, 128-byte ram, 16-bit timers/counters, a 16-bit timer, an asynchronous/synchronous sio interface, motor control 10-bit pwm, two analog comparators, a 6-channel ad converter, a system clock frequency divider, an internal reset and an interrupt feature. features ? flash rom ?? 4608 ? 8 bits (4096 + 512-byte) ? ?? capable of on-board programming with wide range (2.8 to 5.5v) of voltage source. ?? block-erasable in 128 byte units ?? writable in 2-byte units ? ram ?? 128 ? 9 bits ? package form ?? ssop16 (225mil) : lead-/halogen-free type ordering number : ena2055a cmos ic 4.5k-byte from and 128-byte ram integrated 8-bit 1-chip microcontroller * this product is licensed from silicon storage technology, inc. (usa). package dimensions unit : mm (typ) 3178b sanyo : ssop16(225mil) 5.2 4.4 6.4 0.22 0.65 (0.33) 18 9 16 0.5 0.15 1.5max 0.1 (1.3)
LC87F0N04A no.a2055-2/19 ? minimum bus cycle ?? 100.0ns (10mhz at v dd =2.8v to 5.5v) note: the bus cycle time here refers to the rom read speed. ? ports ? normal withstand voltage i/o ports ports i/o direction can be designated in 1 bit units 12(p00 to p03, p1n) ? reset pin 1 ( res ) ? on-chip debugger pin 1 (owp0) ? power pins 2 (v ss , v dd ) ? timers ?? timer 0: 16-bit timer/counter with a capture register. mode 0: 8-bit timer with an 8-bit programmab le prescaler (with an 8-bit capture register) ? 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programma ble prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ?? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-b it prescaler (with toggle outputs) ? 2 channels mode 1: 8-bit pwm with an 8-bit prescaler ? 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm.) ?? base timer 1) the clock is selectable from system clock, and timer 0 prescaler output. 2) interrupts are programmable in 5 different time schemes ? sio ?? sio1: 8-bit asynchronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? ad converter: 10 bits/8 bits ? 6 channels ?? 10/8 bits ad converter resolution selectable ?? auto start function (it links an interrupt factor of motor control pwm) ? remote control receiver circuit (sharing pins with p11, int3) ?? noise rejection function (noise filter time constant selectable from 1 tcyc, 32 tcyc, and 128 tcyc) ? clock output function ?? can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the system clock. ? analog comparator ? 2 channels ?? analog comparator interrupt. ?? analog comparator reference sel ectable (external input / programmable on-chip voltage reference). the voltage reference has 2 ranges with 16-level voltage levels in each range. rang1: cmp1vref1= (cmp1vref-register<3:0> + 1 )/16 ? v dd ? 0.64 cmp2vref2= (cmp2vref-register<3:0> + 1 )/16 ? v dd ? 0.64 rang2: cmp1vref1= (cmp1vref-register<3:0> + 1 )/64 ? v dd ? 0.64 cmp2vref2= (cmp2vref-register<3:0> + 1 )/64 ? v dd ? 0.64 ? mcpwm2: motor control 10bits pwm with full-bridge ?? dead time is programmable. ?? forced stop is possible by the output of th e analog comparator and the int terminals. ?? edge-aligned / center-aligned selectable.
LC87F0N04A no.a2055-3/19 ? watchdog timer ?? can generate the internal reset signal on a timer overflow monitored by the wdt-dedicated low-speed rc oscillation clock (30khz). ?? allows selection of continue, stop, or hold mode operation of the counter on entry into the halt/hold mode. ? interrupts ?? 14 sources, 9 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than th e current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l 4 0001bh h or l int3/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l - 8 0003bh h or l sio1/pwm 9 00043h h or l adc 10 0004bh h or l cmp1/cmp2 ?? priority levels x > h > l ?? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 64levels (the stack is allocated in ram.) ? high-speed multiplication/division instructions ?? 16 bits ? 8 bits (5 tcyc execution time) ?? 24 bits ? 16 bits (12 tcyc execution time) ?? 16 bits ? 8 bits (8 tcyc execution time) ?? 24 bits ? 16 bits (12 tcyc execution time) ? oscillation circuits ?? internal oscillation circuits medium-speed rc oscillation circuit : for system clock (1mhz) high-speed rc oscillation circuit : for system clock (10mhz) low-speed rc oscillation circuit : for watch dog timer (30khz) ? system clock divider function ?? can run on low current. ?? the minimum instruction cycle selectable from 300ns, 600ns, 1.2 ? s, 2.4 ? s, 4.8 ? s, 9.6 ? s, 19.2 ? s, 38.4 ? s, and 76.8 ? s (at a main clock rate of 10mhz). ? internal reset function ?? power-on reset (por) function 1) por reset is generated only at power-on time. 2) the por release level can be selected from 8 levels (1.67v, 1.97v, 2.07v, 2.37v, 2.57v, 2.87v, 3.86v, and 4.35v) through option configuration. ?? low-voltage detection reset (lvd) function 1) lvd and por functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) the use / disuse of the lvd function and the low voltage threshold level (7 levels: 1.91v, 2.01v, 2.31v, 2.51v, 2.81v, 3.79v, 4.28v).
LC87F0N04A no.a2055-4/19 ? standby function halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are three ways of resetting the halt mode. (1) setting the reset pin to the low level (2) system resetting by watchdog timer or low-voltage detection (3) occurrence of an interrupt hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the rc oscillators automatically stop operation. 2) there are four ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) system resetting by watchdog timer or low-voltage detection (3) having an interrupt source estab lished at either int0, int1, int2 * int0 and int1 hold mode reset is available only when level detection is set. ? on-chip debugger ?? supports software debugging with the ic mounted on the target board. ? data security function (flash versions only) ?? protects the program data stored in flash memory from unauthorized read or copy. note: this data security function does not necessarily provide absolute data security. ? development tools ?? on-chip-debugger : tcb87 typec + LC87F0N04A ? programming boards package programming boards ssop16(225mil) w87f0ns ? flash rom programmer maker model supported version device flash support group, inc. (fsg) single programmer af9709/af9709b/af9709c (including ando electric co., ltd. models) rev 03.28 or later 87f008su (3b247) gang programmer af9723/af9723b(main body) (including ando electric co., ltd. models) - - af9833(unit) (including ando electric co., ltd. models) - - sanyo single/gang programmer skk / skk type b (sanyofws) application version 1.07 or later chip data version 2.40 or later lc87f0n04 gang programmer skk-4g (sanyofws) in-circuit/gang programmer skk-dbg type c (sanyofws) application version 1.07 or later chip data version 2.40 or later for information about af-series: flash support group, inc. tel: +81-53-459-1050 e-mail: sales@j-fsg.co.jp
LC87F0N04A no.a2055-5/19 pin assignment sanyo: ssop16(225mil) ?lead-/halogen-free type? ssop16 name ssop16 name 1 res 9 p14/si1/sb1/int0/t0lcp 2 v ss 1 10 p15/sck1/int1/t0hcp/cmp2o 3 owp0 11 p16/an4/t1pwml/cmp2ib(+) 4 v dd 1 12 p17/an5/t1pwmh/cmp2ia(-)/buz 5 p10/an0/int2/t0lcp/t0in 13 p00/mp2ot0 6 p11/an1/int3/t0hcp/t0in/cmp1ib(+) 14 p01/ mp2ot0 7 p12/an2/cmp1ia(-) 15 p02/mp2ot1/cko 8 p13/so1/an3/cmp1o 16 p03/ mp2ot1 res v ss 1 owp0 v dd 1 p10/an0/int2/t0lcp/t0in p11/an1/int3/t0hcp/t0in/cmp1ib(+) p12/an2/cmp1ia(-) p13/so1/an3/cmp1o 16 15 14 13 12 11 10 9 p03/ mp2ot1 p02/mp2ot1/cko p01/ mp2ot0 p00/mp2ot0 p17/an5/t1pwmh/buz/cmp2ia(-) p16/an4/t1pwml/cmp2ib(+) p15/sck1/int1/t0hcp/cmp2o p14/si1/sb1/int0/t0lcp 1 2 3 4 5 6 7 8 LC87F0N04A top view
LC87F0N04A no.a2055-6/19 system block diagram interrupt control standby control ir pla bus interface port 0 port 1 sio1 timer 0 timer 1 adc int0-2 int3 (noise filter) alu flash rom pc acc b register c register psw rar ram stack pointer base timer mcpwm2 on-chip debugger clock generator rc mrc reset control reset circuit (lvd/por) wdt res comparator
LC87F0N04A no.a2055-7/19 pin description pin name i/o description option v ss 1 - - power supply pin no v dd 1 - + power supply pin no port 0 i/o ? 4-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? pin functions p00: mp2ot0(pwm output) p01: mp2ot0 (pwm output) p02: mp2ot1(pwm output) / system clock output p03: mp2ot1 (pwm output) yes p00 to p03 port 1 i/o ? 8-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? pin functions p10: an0(ad converter input) / int2 input / hold reset input / timer 0 event input / timer 0l capture input p11: an1(ad converter input) / int3 input (with noise filter) / timer 0 event input / timer 0h capture input / cmp1(+) input p12: an2(ad converter input) / cmp1(-) input p13: sio1 data output / an3(ad converter input) / cmp1 output p14: sio1 data input / bus i/o / int0 input / hold rese t input / timer 0l capture input p15: sio1 clock i/o / int1 input / hold reset input / timer 0h capture input / cmp2 output p16: timer 1pwml output / cmp2(+) input / an4(ad converter input) p17: timer 1pwmh output / beeper output / cmp2(-) input / an5(ad converter input) interrupt acknowledge type yes p10 to p17 rising falling rising & falling h level l level int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable owp0 i/o on-chip debugger (exclusive pin) no res i/o external reset input / internal reset output no
LC87F0N04A no.a2055-8/19 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor p00 to p03 p10 to p17 1 bit 1 cmos programmable 2 nch-open drain programmable user option table option name option to be applied on flash-rom ve rsion option selected in units of option selection port output type p00 to p03 ? 1 bit cmos nch-open drain p10 to p17 ? 1 bit cmos nch-open drain low-voltage detection reset function detect function ? - enable:use disable:not used detect level ? - 7-level power-on reset function power-on reset level ? - 8-level recommended unused pin connections port name recommended unused pin connections board software p00 to p03 open output low p10 to p17 open output low on-chip debugger pin connection requirements install and connect a limiting resistor (100 ? ) to the on-chip debugger dedicated pin (owp0) on the user board and pull the pin down (100k ? ). it is recommended to install a dedicated connector to accept the cable to the debugging tool (tcb87 type c). the connector must accommodate three lines, i.e., v ss 1, owp0, and v dd 1. 100k ? owp0 v ss 1 v dd 1 100 ?
LC87F0N04A no.a2055-9/19 absolute maximum ratings at ta = 25 ? c, v ss 1 =0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit maximum supply voltage v dd max v dd 1 -0.3 +6.5 v input voltage v i res -0.3 v dd +0.3 input/output voltage v io ports 0, 1 -0.3 v dd +0.3 high level output current peak output current ioph(1) ports 0, 1 cmos output select per 1 applicable pin -10 ma mean output current (note 1-1) iomh(1) ports 0, 1 cmos output select per 1 applicable pin -7.5 total output current ? ioah(1) ports 0 total of all applicable pins -25 ? ioah(2) ports 1 total of all applicable pins -25 low level output current peak output current iopl(1) ports0, 1 per 1 applicable pin 20 mean output current (note 1-1) ioml(1) ports 0, 1 per 1 applicable pin 15 total output current ? ioal(1) ports 0 total of all applicable pins 45 ? ioal(2) ports 1 total of all applicable pins 45 power dissipation pdmax ssop16 ta=-40 to +85 ? c package with thermal resistance board (note 1-2) 238 mw operating ambient temperature topr -40 +85 ? c storage ambient temperature tstg -55 +125 note 1-1: the mean output current is a mean value measured over 100ms. note 1-2: semi standards ther mal resistance board (size: 76.1 ? 114.3 ? 1.6tmm, glass epoxy) is used. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LC87F0N04A no.a2055-10/19 allowable operating conditions at ta = -40 ? c to +85 ? c, v ss 1 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit operating supply voltage v dd (1) v dd 1 0.291 ? s ? tcyc ? 200 ? s 2.8 5.5 v memory sustaining supply voltage v hd v dd 1 ram and register contents sustained in hold mode. 2.0 high level input voltage v ih (1) ports 1 2.8 to 5.5 0.3v dd +0.7 v dd v ih (2) ports 0 2.8 to 5.5 0.3v dd +0.7 v dd v ih (3) res 2.8 to 5.5 0.75v dd v dd low level input voltage v il (1) ports 1 4.0 to 5.5 v ss 0.1v dd +0.4 2.8 to 4.0 v ss 0.2v dd v il (2) ports 0 4.0 to 5.5 v ss 0.15v dd +0.4 2.8 to 4.0 v ss 0.2v dd v il (3) res 2.8 to 5.5 v ss 0.25v dd instruction cycle time (note 2-1) tcyc 2.8 to 5.5 0.291 200 ? s oscillation frequency range fmmrc(1) internal high-speed rc oscillation. (note 2-2) 2.8 to 5.5 9.7 10.0 10.3 mhz fmmrc(2) internal high-speed rc oscillation. ta=0 ? c to 85 ? c (note 2-2) 2.8 to 5.5 9.75 10.0 10.25 mhz fmrc internal medium-speed rc oscillation 2.8 to 5.5 0.5 1.0 2.0 mhz fmsrc internal slow-speed rc oscillation for watchdog timer. 2.8 to 5.5 15 30 60 khz note 2-1: relationship between tcyc and oscillation frequency is 3/fmmrc at a division ratio of 1/1 and 6/fmmrc at a division ratio of 1/2. note 2-2: when switching the system clock, allow an oscillation stabilization time of 100 ? s or longer after the high-speed rc oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.
LC87F0N04A no.a2055-11/19 electrical characteristics at ta = -40 ? c to +85 ? c, v ss 1 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high level input current i ih (1) ports 0, 1 res output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 2.8 to 5.5 1 ? a low level input current i il (1) ports 0, 1 res output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 2.8 to 5.5 -1 high level output voltage v oh (1) ports 0, 1 i oh =-1ma 4.5 to 5.5 v dd -1 v v oh (2) i oh =-0.35ma 2.8 to 5.5 v dd -0.4 v oh (3) port0 (note 3-1) i oh =-6ma 4.5 to 5.5 v dd -1 v oh (4) i oh =-1.4ma 2.8 to 5.5 v dd -0.4 low level output voltage v ol (1) ports 0, 1 i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.4ma 2.8 to 5.5 0.4 pull-up resistance rpu(1) ports 0, 1 v oh =0.9v dd 4.5 to 5.5 15 35 80 k ? rpu(2) 2.8 to 4.5 18 50 230 hysteresis voltage vhys p10(int2), p11(int3), p14,p15, res 2.8 to 5.5 0.1 v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 ? c 2.8 to 5.5 10 pf note 3-1: when ports0 selected mcpwm2.
LC87F0N04A no.a2055-12/19 sio1 serial i/o characteristics at ta = -40 ? c to +85 ? c, v ss 1 = 0v (note 4) parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(3) sck1(p15) ? see fig. 4. 2.8 to 5.5 2 tcyc low level pulse width tsckl(3) 1 high level pulse width tsckh(3) 1 output clock frequency tsck(4) sck1(p15) ? cmos output selected ? see fig. 4. 2.8 to 5.5 2 low level pulse width tsckl(4) 1/2 tsck high level pulse width tsckh(4) 1/2 serial input data setup time tsdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 4. 2.8 to 5.5 0.05 ? s data hold time thdi(2) 0.05 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 4. 2.8 to 5.5 (1/2)tcyc +0.08 note 4: these specifications are theoretical values. add margin depending on its use. pulse input conditions at ta = -40 ? c to +85 ? c, v ss 1 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high/low level pulse width tpih(1) tpil(1) int0(p14), int1(p15), int2(p10) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.8 to 5.5 1 tcyc tpih(2) tpil(2) int3(p11) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.8 to 5.5 2 tpih(3) tpil(3) int3(p11) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.8 to 5.5 64 tpih(4) tpil(4) int3(p11) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.8 to 5.5 256 tpil(5) res ? resetting is enabled. 2.8 to 5.5 200 s
LC87F0N04A no.a2055-13/19 ad converter characteristics at v ss 1 = 0v <10bits ad converter mode/ta = -40 ? c to +85 ? c > parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an0(p10) to an3(p13) an4(p16) an5(p17) 2.8 to 5.5 10 bit absolute accuracy et (note 6-1) 2.8 to 5.5 ? 4 lsb conversion time tcad ? see conversion time calculation formulas. (note 6-2) 4.0 to 5.5 7.8 65.6 ? s 2.8 to 5.5 15 65.6 analog input voltage range vain 2.8 to 5.5 v ss v dd v analog port input current iainh vain=v dd 2.8 to 5.5 1 ? a iainl vain=v ss 2.8 to 5.5 -1 <8bits ad converter mode/ta = -40 ? c to +85 ? c > parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an0(p10) to an3(p13) an4(p16) an5(p17) 2.8 to 5.5 8 bit absolute accuracy et (note 6-1) 2.8 to 5.5 ? 1.5 lsb conversion time tcad ? see conversion time calculation formulas. (note 6-2) 4.0 to 5.5 2.85 25.0 ? s 2.8 to 5.5 5.5 25.0 analog input voltage range vain 2.8 to 5.5 v ss v dd v analog port input current iainh vain=v dd 2.8 to 5.5 1 ? a iainl vain=v ss 2.8 to 5.5 -1 conversion time cal culation formulas: 10bits ad converter mode: tcad(conversion time) = ((40/(ad division ratio))+2) ? (1/3) ? tcyc 8bits ad converter mode: tcad(conversion time) = ((28/(ad division ratio))+2) ? (1/3) ? tcyc external oscillation (fmmrc) operating supply voltage range (v dd ) system division ratio (sysdiv) cycle time (tcyc) ad division ratio (addiv) ad conversion time (tcad) 10bit ad 8bit ad 10bit ad 8bit ad 10mhz 4.0v to 5.5v 1/1 300ns 1/2 1/1 8.5 ? s 2.9 ? s 2.8v to 5.5v 1/1 300ns 1/4 1/2 17 ? s 5.8 ? s note 6-1: the quantization error (1/2lsb ) must be excluded from the absolute accuracy. the absolute accuracy must be measured in the microcontroller's state in which no i/o operations occur at the pins adjacent to the analog input channel. note 6-2: the conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. the conversion time is 2 times the normal-time conversion time when: ?? the first ad conversion is performed in the 10 -bit ad conversion mode after a system reset. ?? the first ad conversion is performed after the ad conversion mode is switched from 8-bit to 10-bit conversion mode.
LC87F0N04A no.a2055-14/19 power-on reset (por) characteristics at ta = -40 ? c to +85 ? c, v ss 1 = 0v parameter symbol pin/remarks conditions specification option selected voltage min typ max unit por release voltage porrl ? select from option. (note 7-1) 1.67v 1.55 1.67 1.79 v 1.97v 1.85 1.97 2.09 2.07v 1.95 2.07 2.19 2.37v 2.25 2.37 2.49 2.57v 2.45 2.57 2.69 2.87v 2.75 2.87 2.99 3.86v 3.73 3.86 3.99 4.35v 4.21 4.35 4.49 detection voltage unknown state pouks ? see fig. 6. (note 7-2) 0.7 0.95 power supply rise time poris ? power supply rise time from 0v to 1.6v. 100 ms note7-1: the por release level can be selected out of 8 levels only when the lvd reset function is disabled. note7-2: por is in an unknown state before transistors start operation. low voltage detection reset (lvd) characteristics at ta = -40 ? c to +85 ? c, v ss 1=0v parameter symbol pin/remarks conditions specification option selected voltage min typ max unit lvd reset voltage (note 8-2) lvdet ? select from option. (note 8-1) (note 8-3) ? see fig. 7. 1.91v 1.81 1.91 2.01 v 2.01v 1.91 2.01 2.11 2.31v 2.21 2.31 2.41 2.51v 2.41 2.51 2.61 2.81v 2.71 2.81 2.91 3.79v 3.69 3.79 3.89 4.28v 4.18 4.28 4.38 lvd hysteresys width lvhys 1.91v 55 mv 2.01v 55 2.31v 55 2.51v 55 2.81v 60 3.79v 65 4.28v 65 detection voltage unknown state lvuks ? see fig. 7. (note 8-4) 0.7 0.95 v low voltage detection minimum width (reply sensitivity) tlvdw ? lvdet-0.5v ? see fig. 8. 0.2 ms note8-1: the lvd reset level can be selected out of 7 levels only when the lvd reset function is enabled. note8-2: lvd reset voltage specification values do not include hysteresis voltage. note8-3: lvd reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. note8-4: lvd is in an unknown state before transistors start operation.
LC87F0N04A no.a2055-15/19 comparator characteristics at ta = -40 ? c to +85 ? c, v ss 1 = 0v parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit input common- mode voltage (note9-1) vcmin p12(cmp1ia), p11(cmp1ib), p17(cmp2ia), p16(cmp2ib) 2.8 to 5.5 v ss v dd -1.5v v offset voltage vcpoff(1) p12(cmp1ia), p11(cmp1ib), p17(cmp2ia), p16(cmp2ib) ? input common-mode voltage range ? cmp1 minus input = cmp1ia ? cmp2 minus input = cmp2ia 2.8 to 5.5 ? 20 mv vcpoff(2) p12(cmp1ia), p11(cmp1ib), p17(cmp2ia), p16(cmp2ib) ? input common-mode voltage range ? cmp1 minus input = cmp1vref (note9-2) ? cmp2 minus input = cmp2 vref (note9-2) 2.8 to 5.5 ? 40 mv cmp response speed tcrt p13(cmp1o), p15(cmp2o) ? input common-mode voltage range ? input amplitude=100mv, over drive=50mv ? cmp1 minus input = cmp1ia ? cmp2 minus input = cmp2ia 2.8 to 5.5 200 ns note9-1: when v dd =5v, input voltage is effective from 0 to 3.5v. note9-2: rang1: cmp1vref1= (cmp1vref-register<3:0> + 1)/16 ? v dd ? 0.64 cmp2vref2= (cmp2vref-register<3:0> + 1)/16 ? v dd ? 0.64 rang2: cmp1vref1= (cmp1vref-register<3:0> + 1)/64 ? v dd ? 0.64 cmp2vref2= (cmp2vref-register<3:0> + 1)/64 ? v dd ? 0.64 *: range1/range2 setting by a register is common to comparators 1 and 2.
LC87F0N04A no.a2055-16/19 consumption current characteristics at ta = -40 ? c to +85 ? c, v ss 1 = 0v parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit normal mode consumption current (note 10-1) (note 10-2) iddop(1) v dd 1 ? internal medium speed rc oscillation stopped. ? system clock set to internal high speed rc oscillation(10mhz). ? 1/1 frequency division ratio 2.8 to 5.5 3.4 4.8 ma iddop(2) ? internal high speed rc oscillation stopped. ? system clock set to internal medium speed rc oscillation. ? 1/2 frequency division ratio 2.8 to 5.5 0.2 0.4 halt mode consumption current (note 10-1) (note 10-2) iddhalt(1) v dd 1 ? halt mode ? internal medium speed rc oscillation stopped. ? system clock set to internal high speed rc oscillation(10mhz). ? 1/1 frequency division ratio 2.8 to 5.5 1.6 2.3 ma iddhalt(2) v dd 1 ? halt mode ? internal high speed rc oscillation stopped. ? system clock set to internal medium speed rc oscillation. ? 1/2 frequency division ratio 2.8 to 5.5 0.10 0.19 hold mode consumption current (note 10-1) (note 10-2) (note 10-3) iddhold(1) v dd 1 hold mode 2.8 to 5.5 0.03 32 ? a iddhold(2) hold mode ? lvd option selected 2.8 to 5.5 3 35 note10-1: values of the consumption current do not include cu rrent that flows into the output transistors and internal pull-up resistors. note10-2: the consumption current values do not includ e operational current of lvd function if not specified. note10-3: the amplifier / comparator circuit operates in the hold mode. f-rom programming characteristics at ta = +10 ? c to +55 ? c, v ss 1 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? only current of the flash block. 2.8 to 5.5 5 10 ma programming time tfw(1) ? erasing time 2.8 to 5.5 20 30 ms tfw(2) ? programming time 40 60 ? s figure 1 ac timing measurement point 0.5v dd
LC87F0N04A no.a2055-17/19 figure 2 reset time figure 3 reset circuit c res v dd r res res note: external circuits for reset may vary depending on the usage of por and lvd. please refer to the user?s manual for more information. power supply res internal medium speed rc oscillation operating mode reset time tpil ( 5 ) unpredictable reset instruction execution reset time v dd operating v dd lower limit 0v
LC87F0N04A no.a2055-18/19 figure 4 serial i/o output waveforms figure 5 pulse input timing signal waveform figure 6 waveform observed when only por is used (lvd not used) (reset pin: pull-up resistor r res only) ? the por function generates a reset only wh en power is turned on starting at the v ss level. ? no stable reset will be generated if power is turned on again when the power level does not go down to the v ss level as shown in (a). if such a case is an ticipated, use the lvd function together with the por function or implement an external reset circuit. ? a reset is generated only when the power level goes down to the v ss level as shown in (b) and power is turned on again after this condition continues for 100 ? s or longer. di0 di7 di2 di3 di4 di5 di6 do0 do7 do2 do3 do4 do5 do6 di1 do1 sioclk: datain: dataout: dataout : datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tpil tpih por release voltage ( porrl ) v dd res unknown-state ( pouks ) (a) (b) reset period reset period 100 ?
LC87F0N04A no.a2055-19/19 figure 7 waveform observed when both por and lvd functions are used (reset pin: pull-up resistor r res only) ? resets are generated both when power is tu rned on and when the power level lowers. ? a hysteresis width (lvhys) is provided to prevent the repetitions of reset releas e and entry cycles near the detection level. figure 8 low voltage detection minimum width (example of momentary power loss/voltage variation waveform) v dd res lvd hysteresis width (lvhys) unknown-state ( lvuks ) reset period reset period reset period lvd release voltage (lvdet+lvhys) lvd reset voltage (lvdet) v dd lvd reset voltage tlvdw v ss lvd release voltage lvdet-0.5v ps on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use a s components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applica tion in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for an y such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and dis tributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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